1. Field of the Invention
The present invention generally relates to triggering a debugging unit, and in particular, a microprocessor configured in accordance with an instruction set architecture for transitioning a debugging unit between a plurality of operating states as directed by trigger instruction signals within an instruction stream.
2. Description of the Related Art
The arrangement of components on an integrated circuit increases in complexity with each improvement in the manufacturing capability of constructing additional transistors onto smaller chips. Thus, in order to meet market demand, adequate and timely testing and debugging of integrated circuits has become a priority.
Currently, there exist several methods of testing and debugging components of an integrated circuit by controlling and/or monitoring a storage of trace data by a debugging unit. One method includes marking instruction addresses of a sequence of operating instructions that are suspected of generating a problem within the integrated circuit. A storage of trace data commences upon an execution of the suspected operating instructions, and ceases after the execution of the suspected operating instructions. Another method includes marking an operating instruction to commence a storage of trace data upon the execution of the operating instruction, and marking a subsequent operating instruction to cease a storage of trace data upon the execution of the subsequent operating instruction. An additional method includes detecting a particular pattern of trace data being provided via a bus to a trace array. Yet another method includes generating signals internal to a multi-state logic analyzer for controlling an operation of a trace array in selectively storing trace data.
All of the aforementioned methods of testing and debugging components of an integrated circuit have not always produced consistent and reliable results. The computer industry is therefore continually striving to improve upon the monitoring of trace data by a debugging unit.